One problem that is encountered when operating a high performance digital data processor is in providing a sufficient main memory bandwidth to enable a central processor, and an IO controller, to operate at their optimum data transfer rates.
Another problem relates to a tendency of a central processor, for certain types of processing tasks, to make a number of writes to a relatively small region of main memory. If the writes are, for example, byte writes and if the main memory has a word width of a number of bytes, then typically a read-modify-write cycle is executed so as to modify only the intended byte within the word. However, a read-modify-write cycle requires a significantly longer time to accomplish than a conventional full word write, where all bytes within a word are written with the same write operation. As a result, the central processor may be required to wait until a previous read-modify-write operation is completed before terminating an on-going write request. As can be appreciated, it would be desirable to reduce the number of executed read-modify-write cycles so as to improve the efficiency of the data processor.
Another, related problem concerns the operation of the IO controller when transferring large blocks of data to or from the main memory. That is, it would be desirable to operate the main memory in such a manner that the IO controller is not required to incur wait states during memory writes or reads.